Joseph M. Steigerwald

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Peng Bai, C. Auth, S. Balakrishnan et al. · 2005 · 230 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15

Chemical processes in the chemical mechanical polishing of copper

Joseph M. Steigerwald, S. P. Murarka, R.J. Gutmann et al. · Materials Chemistry and Physics · 1995 · 195 citations

Materials Science, Chemical Engineering, Engineering +7

Pattern Geometry Effects in the Chemical‐Mechanical Polishing of Inlaid Copper Structures

Joseph M. Steigerwald, R. Zirpoli, S. P. Murarka et al. · Journal of The Electrochemical Society · 1994 · 128 citations

Materials Science, Inlaid Copper Structures, Pattern Geometry Effects +15

A high performance 180 nm generation logic technology

Shih‐Chi Yang, Sally Ahmed, B. Arcot et al. · 2002 · 89 citations

Low-power Electronics, Materials Engineering, Electrical Engineering +13

Contact and via structures with copper interconnects fabricated using dual Damascene technology

S. Lakshminarayanan, Joseph M. Steigerwald, D.T. Price et al. · IEEE Electron Device Letters · 1994 · 61 citations

Chemical-mechanical Polishing, Engineering, Mechanical Engineering +22