G. Chabanne

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm² 6T-SRAM bitcell

C. Fenouillet-Béranger, J. Todeschini, Jean-Christophe Le-Denmat et al. · 2007 · 61 citations

Engineering, Computer Engineering, Electrical Engineering +15

Selective etching of Si1−xGex versus Si with gaseous HCl for the formation of advanced CMOS devices

N. Loubet, T. Kormann, G. Chabanne et al. · Thin Solid Films · 2008 · 29 citations

Engineering, Materials Engineering, Materials Science +17

Advanced FD-SOI and Beyond Low Temperature SmartCut™ Enables High Density 3-D SoC Applications

W. Schwarzenbach, Nicolas Daval, Christophe Maleville et al. · IEEE Journal of the Electron Devices Society · 2019 · 14 citations · Full text

Engineering, Electrical Engineering, Materials Science +17