D. Lionberger

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

J. Kavalieros, Barry M. Doyle, Suman Datta et al. · 2006 · 220 citations

Engineering, Electrical Engineering, Materials Science +17

30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

R. Chau, J. Kavalieros, B. Roberds et al. · 2002 · 110 citations

Engineering, Electrical Engineering, Microelectronics +16

A 50 nm depleted-substrate CMOS transistor (DST)

R. Chau, J. Kavalieros, Barry M. Doyle et al. · 2002 · 101 citations

Engineering, Electrical Engineering, Microelectronics +14

High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

R. Pillarisetty, B. Chu-Kung, S. Corcoran et al. · 2010 · 90 citations

Engineering, Electrical Engineering, Physics +17

Impact of line-width roughness on Intel's 65-nm process devices

Manish Chandhok, Suman Datta, D. Lionberger et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2007 · 15 citations

Engineering, Computer Engineering, Electrical Engineering +17