R. Pillarisetty - Concepedia

Concepedia

Author

R. Pillarisetty

Intel (United States)

Also Known As

Borjans, Felix, Pillarisetty, R., R. PILLARISETTY, R. Pillarisetty, Ravi Pillarisetty, Zietz, Otto K.

52

Publications

1.9K

Citations

18

H-Index

56

Concepts

All Affiliations

Intel (United States)Princeton University IQE (United States)QuTech Delft University of Technology

RP

About

R. Pillarisetty is an author at Intel (United States) specializing in engineering, applied physics, and physics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	16	1.6K
2	Applied Physics	13	15	1.1K
3	Electrical Engineering	11	12	958
4	Natural Sciences	4	4	150
5	Computer Engineering	3	3	76

R. Pillarisetty

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23

Publications

1.9K

Citations

18

H-Index

	Year	Citations
Academic and industry research progress in germanium nanodevices R. Pillarisetty Nature Materials ScienceNanoscale ScienceNanoscale SystemEngineeringNanomaterials	2011	520
Fabrication, characterization, and physics of III&#x2013;V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing G. Dewey, B. Chu-Kung, J. Boardman, Semiconductor TechnologyV HeterojunctionElectrical EngineeringSteep Sub-threshold SwingEngineering	2011	331
Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation M. Radosavljević, G. Dewey, Dipanjan Basu, SemiconductorsSemiconductor TechnologyElectrical EngineeringElectronic DevicesHigh-k Gate Dielectric	2011	136
Probing single electrons across 300-mm spin qubit wafers Samuel F. Neyens, Otto Zietz, Thomas F. Watson, Nature	2024	112
High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications M. Radosavljević, T. Ashley, A. D. Andreev, Semiconductor TechnologyElectrical EngineeringLogic ApplicationsEngineeringSemiconductor Device	2008	99
Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications M. Radosavljević, G. Dewey, J. M. Fastenau, Semiconductor TechnologyElectrical EngineeringHigh-k Gate DielectricEngineeringPhysics	2010	93
High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III&#x2013;V CMOS architecture R. Pillarisetty, B. Chu-Kung, S. Corcoran, EngineeringApplied AlgebraSemiconductor DeviceElectronic EngineeringField Effect Transistor	2010	89
Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications G. Dewey, Mantu K. Hudait, Kangho Lee, IEEE Electron Device Letters	2008	76
Heterogeneous integration of enhancement mode in<sub>0.7</sub>ga<sub>0.3</sub>as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications Mantu K. Hudait, G. Dewey, Suman Datta, Si SubstrateEngineeringDevice IntegrationLow Supply VoltageOptoelectronic Devices	2007	71
Frictional Drag between Two Dilute Two-Dimensional Hole Layers R. Pillarisetty, Hwayong Noh, D. C. Tsui, Physical Review Letters EngineeringPhysicsFluid MechanicsMechanical EngineeringApplied Physics	2002	57

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