Marc Bourcerie

Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2<or=V/sub g/>or=V/sub d/) during hot-carrier stressing of n-MOS transistors

Barry M. Doyle, Marc Bourcerie, J.-C. Marchetaux et al. · IEEE Transactions on Electron Devices · 1990 · 237 citations

Materials Engineering, Semiconductor Technology, Electrical Engineering +13

The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot-carrier stressing of n-MOS transistors

B.S. Doyle, Marc Bourcerie, C. Bergonzoni et al. · IEEE Transactions on Electron Devices · 1990 · 171 citations

Semiconductor Technology, Electrical Engineering, Engineering +12

Relaxable damage in hot-carrier stressing of n-MOS transistors-oxide traps in the near interfacial region of the gate oxide

Marc Bourcerie, B.S. Doyle, J.-C. Marchetaux et al. · IEEE Transactions on Electron Devices · 1990 · 41 citations

Engineering, Silicon On Insulator, Semiconductor Device +16

Application of the floating-gate technique to the study of the n-MOSFET gate current evolution due to hot-carrier aging

J.-C. Marchetaux, Marc Bourcerie, A. Boudou et al. · IEEE Electron Device Letters · 1990 · 30 citations

Device Modeling, Electrical Engineering, Semiconductor Device +14

Dynamic channel hot-carrier degradation of NMOS transistors by enhanced electron-hole injection into the oxide

B.S. Doyle, Marc Bourcerie, J.-C. Marchetaux et al. · IEEE Electron Device Letters · 1987 · 25 citations

Enhanced Electron-hole Injection, Electrical Engineering, Hot-carrier Stressing +11