Ching-Te Chuang - Concepedia

Author

Ching-Te Chuang

National Yang Ming Chiao Tung University

Also Known As

Ching-Te Chuang, Ching-Te K. Chuang, Ching-Te Kent Chuang, Ching-te Chuang

Publications

649

Citations

H-Index

Concepts

All Affiliations

National Yang Ming Chiao Tung University Faraday Technology (Taiwan)IBM Research - Thomas J. Watson Research Center IBM (United States)

About

Ching-Te Chuang is an author at National Yang Ming Chiao Tung University specializing in electrical engineering, microelectronics, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	10	541
2	Electrical Engineering	10	10	541
3	Computer Engineering	9	9	528
4	Applied Physics	3	3	81
5	Materials Science	1	1	13

Ching-Te Chuang

Publications

541

Citations

H-Index

Page 1

	Year	Citations
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, IEEE Journal of Solid-State Circuits Non-volatile MemoryElectrical EngineeringSubthreshold SramEngineeringVlsi Design	2012	171
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, IEEE Transactions on Circuits and Systems I Regular Papers Low-power ElectronicsPositive FeedbackElectrical EngineeringNon-volatile MemoryEngineering	2010	137
Floating-body effects in partially depleted SOI CMOS circuits Pong-Fei Lu, Ching-Te Chuang, Ji Jin, IEEE Journal of Solid-State Circuits Hardware SecurityElectrical EngineeringEngineeringVlsi DesignPhysics	1997	77
Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach Ming-Long Fan, Yusheng Wu, Vita Pi‐Ho Hu, IEEE Transactions on Electron Devices Device ModelingRelaxed Device DimensionsElectrical EngineeringNon-volatile MemoryEngineering	2011	42
Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance Aditya Bansal, Rahul Rao, Jae‐Joon Kim, IEEE International Reliability Physics Symposium proceedings Non-volatile MemoryEngineeringVlsi DesignComputer ArchitectureSram Bit-cells	2009	36
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist Chien-Yu Lu, Ching-Te Chuang, Shyh‐Jye Jou, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Non-volatile MemoryEngineeringVlsi DesignEnergy EfficiencyEmerging Memory Technology	2014	32
A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist Chien-Yu Lu, Ming-Hsien Tu, Hwai‐I Yang, IEEE Transactions on Circuits & Systems II Express Briefs Non-volatile MemoryEngineeringVlsi DesignEmerging Memory Technology40-Nm 72-Kb 9T	2012	13
Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs Chang-Hung Yu, Pin Su, Ching-Te Chuang IEEE Electron Device Letters Non-volatile MemoryEngineeringEmerging Memory TechnologyIntegrated CircuitsPhase Change Memory	2016	13
Near-/Sub-V<inf>th</inf> process, voltage, and temperature (PVT) sensors with dynamic voltage selection Ming‐Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Low-power ElectronicsElectrical EngineeringEnergy HarvestingEngineeringSensors	2013	10
Self-Repairing SRAM Using On-Chip Detection and Compensation Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae‐Joon Kim, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Hardware SecurityElectrical EngineeringEngineeringHardware ReliabilitySram Yield Enhancement	2009	10

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