Ming-Chien Tsai

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai et al. · IEEE Journal of Solid-State Circuits · 2012 · 171 citations

Engineering, Computer Engineering, Electrical Engineering +15

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2010 · 138 citations

Engineering, Computer Engineering, Electrical Engineering +17

An All-Digital High-Precision Built-In Delay Time Measurement Circuit

Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 2008 · 52 citations

Engineering, Computer Engineering, Electrical Engineering +17

True hardware random number generation implemented in the 32-nm SOI POWER7+ processor

J. S. Liberty, Anthony Barrera, D. Boerstler et al. · IBM Journal of Research and Development · 2013 · 16 citations

Engineering, Computer Engineering, Electrical Engineering +15