IEEE Transactions on Circuits and Systems I Regular Papers · 2010 · 138 citations · 21 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDynamic Power ReductionLow-noise Circuit DesignLow-power Digital Circuit DesignSubthreshold Circuit DesignMemory Circuit DesignNoise MarginsPositive FeedbackPower ConsumptionStatic MarginStatic Noise MarginStatic Random-access Memory DesignSubthreshold Memory Circuits
In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.
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Stable SRAM cell design for the 32 nm node and beyond
L. Chang, David Fried, J. M. Hergenrother et al. · 2005 · 567 citations
Engineering, Computer Engineering, Electrical Engineering +17