I.-C. Chen

Interface trap-enhanced gate-induced leakage current in MOSFET

I.-C. Chen, C.W. Teng, D. J. Coleman et al. · IEEE Electron Device Letters · 1989 · 99 citations

Device Modeling, Semiconductor Technology, Electrical Engineering +9

Physical oxide thickness extraction and verification using quantum mechanical simulation

C. Bowen, Chenjing L. Fernando, Gerhard Klimeck et al. · 2002 · 56 citations

Materials Science, Materials Engineering, Electrical Engineering +14

A scaled 1.8 V, 0.18 μm gate length CMOS technology: device design and reliability considerations

M. Rödder, S. Aur, I.-C. Chen · 2002 · 32 citations

Low-power Electronics, Pocket Implant, Electrical Engineering +12

A shallow trench isolation study for 0.25/0.18 μm CMOS technologies and beyond

Amitava Chatterjee, J. Esquivel, Soumya Shubhra Nag et al. · 2002 · 28 citations

Low-power Electronics, Electrical Engineering, Engineering +13

Integration of unit processes in a shallow trench isolation module for a 0.25 μm complementary metal–oxide semiconductor technology

Amitava Chatterjee, Inayat Ali, K. Joyner et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 1997 · 27 citations

Unit Processes, Electrical Engineering, Engineering +11