A scaled 1.8 V, 0.18 μm gate length CMOS technology: device design and reliability considerations

Abstract

Device design improvements for scaling to a high performance 1.8 V, 0.18 /spl mu/m gate length CMOS technology are presented. nMOS with nominal I/sub drive/(I/sub drive//sup nom/)=55 /spl mu/A//spl mu/m drive (with t/sub ox//sup acc/=43 /spl Aring/, t/sub ox//sup inv/=49 /spl Aring/ from C-V at V/sub gb/=-4, +2.5V), R/sub sd/<280 /spl Omega/-/spl mu/m, L/sub g//sup min/ (minimum gate length at I/sub off/=1 nA//spl mu/m)=0.16 /spl mu/m, and hot carrier lifetime /spl Gt/10 years is achieved. Increased As HDD dose, pocket implant, and RTA HDD anneal are required for simultaneous high I/sub drive//sup nom/, high carrier velocity vs. DIBL, and L/sub g//sup min/=0.16 /spl mu/m. pMOS with L/sub g//sup min/=0.16 /spl mu/m and with I/sub drive//sup nom/=220 /spl mu//spl alpha///spl mu/m is achieved. BF/sub 2/ HDD plus RTA HDD anneal prior to sidewall deposition to eliminate interstitial enhanced B tail diffusion are utilized to form more abrupt pMOS HDD junctions. Super-steep retrograde (SSR) As channel profile reduces SCE and increases v/sub eff/ (and I/sub drive/) vs. DIBL, but decreases v/sub eff/ (and I/sub drive/) vs. I/sub off/, compared to a non-SSR profile. pMOS (I/sub drive//sup nom/)=220 /spl mu/A//spl mu/m (with non-SSR profile) and nMOS I/sub drive//sup nom/)=550 /spl mu/A//spl mu/m result in a 30% improvement in speed for the 1.8 V, 0.18 /spl mu/m technology compared to a prior 2.5 V, 0.25 /spl mu/m technology.