K. Shono

SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

Taiki Uemura, Y. Tosaka, Hideya Matsuyama et al. · 2010 · 46 citations

Engineering, Vlsi Design, Single Event Transient +19

600 V JEDEC-qualified highly reliable GaN HEMTs on Si substrates

T. Kikkawa, Tsutomu Hosoda, Kenji Imanishi et al. · 2014 · 44 citations

Wide-bandgap Semiconductor, Electrical Engineering, Reliable Gan Hemts +11

Commercialization and reliability of 600 V GaN power switches

T. Kikkawa, Tsutomu Hosoda, K. Shono et al. · 2015 · 36 citations

Reliability, Electrical Engineering, Reliability Engineering +12

Dynamic performances of GaN-HEMT on Si in cascode configuration

Tatsuya Hirose, Miki Imai, K. Joshin et al. · 2014 · 34 citations

Electrical Engineering, Semiconductor Device, Engineering +12

(Invited)<i/>650 Volt GaN Commercialization Reaches Automotive Standards

P. Parikh, Kurt V. Smith, R. Barr et al. · ECS Transactions · 2017 · 23 citations