Taiki Uemura

SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

Taiki Uemura, Y. Tosaka, Hideya Matsuyama et al. · 2010 · 46 citations

Engineering, Vlsi Design, Single Event Transient +19

Multi-Scale Monte Carlo Simulation of Soft Errors Using PHITS-HyENEXSS Code System

Shinichiro Abe, Yukinobu Watanabe, Nozomi Shibano et al. · IEEE Transactions on Nuclear Science · 2012 · 36 citations

Engineering, Simulation, Neutron Incidence +25

Reliability characterization of 10nm FinFET technology with multi-V<inf>T</inf> gate stack for low power and high performance

Minjung Jin, Changze Liu, Jinju Kim et al. · 2016 · 26 citations

Reliability, Low Power, Electrical Engineering +12

Neutron-Induced Soft-Error Simulation Technology for Logic Circuits

Taiki Uemura, Y. Tosaka, Shigeo Satoh · Japanese Journal of Applied Physics · 2006 · 22 citations

Engineering, Mem Testing, Computer Architecture +18

Technology Scaling Trend of Soft Error Rate in Flip-Flops in <inline-formula> <tex-math notation="LaTeX">$1\times$ </tex-math> </inline-formula> nm Bulk FinFET Technology

Taiki Uemura, Soon Young Lee, Udit Monga et al. · IEEE Transactions on Nuclear Science · 2018 · 22 citations

Device Modeling, Electrical Engineering, Engineering +14