SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

Abstract

We have developed a robust latch for achieving high reliability in LSI. The latch can attenuate multi-node single-event-upset (MNSEU) and single event transient on local-clock (SETLC). The robust latch has Dual-clock-buffers (DCB) and Double-height-cell (DHC) technologies. Results on neutron acceleration experiments show that DHC can dramatically attenuate MNSEU and DCB can protect almost SETLC of the latch. In addition, we investigate optimum design in well structure.