Hideya Matsuyama

SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

Taiki Uemura, Y. Tosaka, Hideya Matsuyama et al. · 2010 · 46 citations

Engineering, Vlsi Design, Single Event Transient +19

Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment

Taiki Uemura, Takashi Kato, Hideya Matsuyama et al. · IEEE Transactions on Nuclear Science · 2013 · 20 citations

Engineering, Terrestrial Environment, Ultra-low Voltages +16

Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization With Neutrons and Alpha Particles

Takashi Kato, M. Tampo, Soshi Takeshita et al. · IEEE Transactions on Nuclear Science · 2021 · 20 citations

Engineering, Mcu Characteristics, Muon Irradiation +18

A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 μm/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

S. Nakai, M. Kojima, N. Misawa et al. · 2004 · 19 citations

Engineering, Vlsi Design, Mobile Multimedia Applications +17

Stress migration phenomenon in narrow copper interconnects

Takashi Suzuki, T. Nakamura, Y. Mizushima et al. · Journal of Applied Physics · 2007 · 18 citations · Full text

Engineering, Severe Plastic Deformation, Residual Stress +17