Cyrus Tabery

FinFET scaling to 10 nm gate length

Bin Yu, Leland Chang, Safayet Ahmed et al. · 2003 · 592 citations

Electrical Engineering, Nm Gate Length, Engineering +12

The use of EUV lithography to produce demonstration devices

Bruno LaFontaine, Yunfei Deng, Ryoung-Han Kim et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2008 · 42 citations

Evaluation of OPC quality using automated edge placement error measurement with CD-SEM

Cyrus Tabery, Hidetoshi Morokuma, Akiyuki Sugiyama et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2006 · 28 citations

Engineering, Electron-beam Lithography, Measurement +18

Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer

Thomas I. Wallow, Alden Acheta, Yuansheng Ma et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2007 · 28 citations

Engineering, Electron-beam Lithography, Photoresist Ler +16

Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning

Haoyu Yang, Shuhe Li, Cyrus Tabery et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2020 · 25 citations

Engineering, Machine Learning, Electronic Design Automation +19