Fumihiko Tachibana - Concepedia

Author

Fumihiko Tachibana

Toshiba (Japan)ORCID

Also Known As

F Tachibana, F. Tachibana, Fumihiko TACHIBANA, Fumihiko Tachibana

Publications

273

Citations

H-Index

Concepts

All Affiliations

Toshiba (Japan)

About

Fumihiko Tachibana is an author at Toshiba (Japan) specializing in engineering, computer engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	220
2	Computer Engineering	8	8	210
3	Electrical Engineering	7	7	149
4	Applied Physics	1	1	42
5	Computer Science	1	1	15

Fumihiko Tachibana

Publications

220

Citations

H-Index

Page 1

	Year	Citations
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, H.264 720PSystem On ChipEmbedded Forward-body-biasingEngineering8-Core Media Processor	2008	56
Re-Examination of Impact of Intrinsic Dopant Fluctuations on Static RAM (SRAM) Static Noise Margin Fumihiko Tachibana, Toshiro Hiramoto Japanese Journal of Applied Physics Non-volatile MemoryEngineeringV ThEmerging Memory TechnologyIntrinsic Threshold Voltage	2005	42
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, IEEE Journal of Solid-State Circuits Low-power ElectronicsRandom-variation-tolerant Timing GenerationElectrical EngineeringEngineeringVlsi Design	2011	38
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit Fumihiko Tachibana, Osamu Hirabayashi, Y. Takeyama, IEEE Journal of Solid-State Circuits Low-power ElectronicsActive ModeElectrical EngineeringPower-aware ComputingEngineering	2013	20
A 187.5&#x00B5;Vrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC Jun Deguchi, Fumihiko Tachibana, M. Morimoto, Low-power ElectronicsElectrical EngineeringChip SizeEngineeringCalibration	2013	17
FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision Asuka Maki, Daisuke Miyashita, Kengo Nakata, Convolutional Neural NetworkWeight BitMachine LearningEngineeringHardware Acceleration	2018	15
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Low-power ElectronicsHardware SecurityElectrical EngineeringEngineeringVlsi Design	2008	12
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs Atsushi Kawasumi, Y. Takeyama, Osamu Hirabayashi, Low-power ElectronicsHardware SecurityElectrical EngineeringStatistical MethodWorst-case Timing-generation Scheme	2012	10
Re-examination of Impact of Intrinsic Dopant Fluctuations on SRAM Static Noise Margin Fumihiko Tachibana, Toshiro Hiramoto Electrical EngineeringEngineeringPhysicsBias Temperature InstabilityIntrinsic Dopant Fluctuations	2004	10

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