Y. Le Tiec

Bonded planar double-metal-gate NMOS transistors down to 10 nm

M. Vinet, T. Poiroux, J. Widiez et al. · IEEE Electron Device Letters · 2005 · 128 citations

Alignment Marks, Electrical Engineering, Engineering +7

Silicon carbide on insulator formation using the Smart Cut process [Note 1]

L. Di Cioccio, Y. Le Tiec, F. Letertre et al. · Electronics Letters · 1996 · 120 citations

Silicon carbide on insulator formation by the Smart-Cut® process

L. Di Cioccio, F. Letertre, Y. Le Tiec et al. · Materials Science and Engineering B · 1997 · 97 citations

Materials Science, Materials Engineering, Engineering +5

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

Qianlong Liu, M. Vinet, J. Gimbert et al. · 2013 · 96 citations

Semiconductor Technology, Electrical Engineering, Gate Length +15

Overview of recent direct wafer bonding advances and applications

H. Moriceau, F. Rieutord, Frank Fournel et al. · Advances in Natural Sciences Nanoscience and Nanotechnology · 2011 · 82 citations · Full text

Materials Science, Materials Engineering, Electrical Engineering +15