Venkata Chaitanya Krishna Chekuri

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020 · 90 citations

Hardware Modeling, Engineering, Computer Architecture +16

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · 2019 · 53 citations · Full text

Engineering, Computer Architecture, Hardware Architecture +16

Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO

Arvind Singh, Monodeep Kar, Venkata Chaitanya Krishna Chekuri et al. · IEEE Journal of Solid-State Circuits · 2019 · 51 citations

Engineering, Vlsi Design, Information Security +18

Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs

Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2021 · 35 citations

Engineering, Vlsi Design, Energy Efficiency +20

A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors

Hakki Mert Torun, Huan Yu, Nihar Dasari et al. · 2019 · 33 citations

Model Optimization, Electrical Engineering, Convolutional Neural Network +14