Jinwoo Kim

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020 · 90 citations

Hardware Modeling, Engineering, Computer Architecture +16

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Philip Jacob, Aamir Zia, Okan Erdogan et al. · Proceedings of the IEEE · 2009 · 59 citations

Engineering, Computer Architecture, Memory Processor Chip +16

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · 2019 · 53 citations · Full text

Engineering, Computer Architecture, Hardware Architecture +16

Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs

Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2021 · 35 citations

Engineering, Vlsi Design, Energy Efficiency +20

Overcurrent and Short-Circuit Protection Method using Desaturation Detection of SiC MOSFET

Jinwoo Kim, Younghoon Cho · 2020 · 34 citations

Sic Mosfet, Electrical Engineering, Desaturation Detection Circuit +8