Jinwoo Kim

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020 · 95 citations

Engineering, Computer Engineering, Computer Science +17

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Philip Jacob, Aamir Zia, Okan Erdogan et al. · Proceedings of the IEEE · 2009 · 59 citations

Engineering, Computer Engineering, Computer Science +15

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · 2019 · 56 citations · Full text

Engineering, Computer Engineering, Computer Science +17

Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs

Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2021 · 40 citations

Engineering, Computer Engineering, Electrical Engineering +17

A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors

Hakki Mert Torun, Huan Yu, Nihar Dasari et al. · 2019 · 35 citations

Engineering, Computer Engineering, Electrical Engineering +14