Heechun Park

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020 · 95 citations

Engineering, Computer Engineering, Computer Science +17

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · 2019 · 56 citations · Full text

Engineering, Computer Engineering, Computer Science +17

Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs

Heechun Park, Bon Woong Ku, Kyungwook Chang et al. · 2020 · 25 citations · Full text

Engineering, Computer Engineering, Design +11

Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC

Heechun Park, Jinwoo Kim, Venkata Chaitanya Krishna Chekuri et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2020 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +17

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs

Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park et al. · 2019 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +17