Gauthaman Murali

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020 · 90 citations

Hardware Modeling, Engineering, Computer Architecture +16

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · 2019 · 53 citations · Full text

Engineering, Computer Architecture, Hardware Architecture +16

Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM

Gauthaman Murali, Xiaoyu Sun, Shimeng Yu et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020 · 35 citations

Convolutional Neural Network, Resistive Ram, Engineering +20

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

Yi‐Chen Lu, Sai Pentapati, Lingjun Zhu et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2021 · 11 citations

ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs

Gauthaman Murali, Sandra Maria Shaji, Anthony Agnesina et al. · 2022 · 11 citations

Engineering, Accelerated Design, Electronic Design Automation +24