Arvind Singh

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020 · 90 citations

Hardware Modeling, Engineering, Computer Architecture +16

Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator

Monodeep Kar, Arvind Singh, Sanu Mathew et al. · IEEE Journal of Solid-State Circuits · 2018 · 72 citations

Hardware Security, Low-power Electronics, Electrical Engineering +10

8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator

Monodeep Kar, Arvind Singh, Sanu Mathew et al. · 2017 · 70 citations

Hardware Security, Low-power Electronics, Electrical Engineering +15

Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering

Arvind Singh, Monodeep Kar, Sanu Mathew et al. · IEEE Journal of Solid-State Circuits · 2018 · 69 citations

Hardware Security, Low-power Electronics, Electrical Engineering +9

25.3 A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator

Arvind Singh, Monodeep Kar, Sanu Mathew et al. · 2019 · 53 citations

Hardware Security, Low-power Electronics, Electrical Engineering +14