Bharani Chava

Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery

Julien Ryckaert, Anshul Gupta, Anne Jourdain et al. · 2019 Electron Devices Technology and Manufacturing Conference (EDTM) · 2019 · 53 citations

Engineering, Energy Efficiency, Power Optimization (Eda) +17

High-Aspect-Ratio Ruthenium Lines for Buried Power Rail

Anshul Gupta, Shreya Kundu, Lieve Teugels et al. · 2018 · 48 citations

Materials Science, Low-power Electronics, Electrical Engineering +14

Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu$ TSVs

Md Obaidul Hossen, Bharani Chava, Geert Van der Plas et al. · IEEE Transactions on Electron Devices · 2019 · 46 citations

Power Engineering, Engineering, Vlsi Design +21

DTCO at N7 and beyond: patterning and electrical compromises and opportunities

Julien Ryckaert, Praveen Raghavan, P. Schuddinck et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2015 · 32 citations

Engineering, Vlsi Design, Vertical Transistor +16

Standard cell design in N7: EUV vs. immersion

Bharani Chava, David del Rio, Yasser Sherazi et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2015 · 30 citations

Engineering, Electron-beam Lithography, Microscopy +18