Jakub Janicki

EDT Bandwidth Management in SoC Designs

Jakub Janicki, Mark Kassab, Grzegorz Mrugalski et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2012 · 20 citations

Engineering, Electronic Design, Computer Architecture +17

EDT bandwidth management - Practical scenarios for large SoC designs

Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng et al. · 2013 · 17 citations

Engineering, Electronic Design, Computer Architecture +21

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

Jakub Janicki, Jerzy Tyszer, A. Dutta et al. · 2011 · 16 citations

Hardware Security, Electrical Engineering, Engineering +14

Dynamic channel allocation for higher EDT compression in SoC designs

Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee et al. · 2010 · 16 citations

Engineering, Vlsi Design, Computer Architecture +21

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating

Elham Moghaddam, Janusz Rajski, S.M. Reddy et al. · 2011 · 12 citations

Engineering, Measurement, Computer Architecture +18