2024 · 10 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignComplementary Metal-oxide-semiconductor TechnologyDevice ScalingIntegrated Circuit DesignLow-power Digital Circuit DesignPower OptimizationPower-aware DesignCmos ScalingComplementary Metal-oxide-semiconductor ScalingDevice OptimizationLogic OptimizationPower-performance-area TradeoffsProcess Complexity AnalysisScalabilityTechnology Scaling
Complementary FET (CFET) device architecture with stacked n-/p-FETs is an outstanding option, promising power, performance, area scalability in the post-FinFET device era. Among several options, the double-row (DR) CFET architecture leads to reduced process complexity in the middle-of-line (MOL), and gains in logic and SRAM area, by scaling to 3.5Tracks x CPP per 2 FETs. Projections show ~40% area and ~12% power scaling potential.
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VLSI 85: VLSI design of digital systems
Microprocessors and Microsystems · 1986 · 151 citations
Engineering, Computer Engineering, Electrical Engineering +14
VLSI'87: VLSI design of digital systems
Integration · 1989 · 134 citations
Engineering, Computer Engineering, Electrical Engineering +14