Dawit Burusie Abdi - Concepedia

Author

Dawit Burusie Abdi

Indian Institute of Technology Delhi

Also Known As

D. Abdi, Damon Abdi, Dawit Abdi, Dawit B. Abdi, Dawit Burusie Abdi

Publications

874

Citations

H-Index

Concepts

All Affiliations

Indian Institute of Technology Delhi IMEC M S Ramaiah University of Applied Sciences

About

Dawit Burusie Abdi is an author at Indian Institute of Technology Delhi specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	774
2	Electrical Engineering	8	8	662
3	Applied Physics	6	6	603
4	Biomedical Engineering	1	1	112
5	Computer Engineering	1	1	21

Dawit Burusie Abdi

Publications

812

Citations

H-Index

Page 1

	Year	Citations
Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain Dawit Burusie Abdi, M. Jagadesh Kumar IEEE Journal of the Electron Devices Society Device ModelingSemiconductor TechnologyElectrical EngineeringSemiconductor DeviceEngineering	2014	318
In-Built N<sup>&#x002B;</sup> Pocket p-n-p-n Tunnel Field-Effect Transistor Dawit Burusie Abdi, M. Jagadesh Kumar IEEE Electron Device Letters SemiconductorsSemiconductor TechnologyElectrical EngineeringSemiconductor DeviceEngineering	2014	159
Dielectric modulated overlapping gate-on-drain tunnel-FET as a label-free biosensor Dawit Burusie Abdi, M. Jagadesh Kumar Superlattices and Microstructures Label-free BiosensorImplantable SensorEngineeringBioelectronicsBiomedical Engineering	2015	112
Dopingless PNPN tunnel FET with improved performance: Design and analysis Mamidala Saketh Ram, Dawit Burusie Abdi Superlattices and Microstructures Materials ScienceElectrical EngineeringImproved PerformanceEngineeringTunneling Microscopy	2015	60
PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis Dawit Burusie Abdi, M. Jagadesh Kumar Superlattices and Microstructures Electrical EngineeringPnpn Tunnel FetEngineering	2015	38
2-D Threshold Voltage Model for the Double-Gate p-n-p-n TFET With Localized Charges Dawit Burusie Abdi, M. Jagadesh Kumar IEEE Transactions on Electron Devices Device ModelingElectrical EngineeringDouble-gate P-n-p-n TfetEngineeringPhysics	2016	29
Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node Hsiao-Hsuan Liu, Shairfe Muhammad Salahuddin, Dawit Burusie Abdi, IEEE Transactions on Electron Devices Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringResistance-dominated Technology Node	2022	21
Single Grain Boundary Dopingless PNPN Tunnel FET on Recrystallized Polysilicon: Proposal and Theoretical Analysis Mamidala Saketh Ram, Dawit Burusie Abdi IEEE Journal of the Electron Devices Society Materials EngineeringMaterials ScienceElectrical EngineeringDevice ModelingRecrystallized Polysilicon	2015	20
Single Grain Boundary Tunnel Field Effect Transistors on Recrystallized Polycrystalline Silicon: Proposal and Investigation Mamidala Saketh Ram, Dawit Burusie Abdi IEEE Electron Device Letters SemiconductorsDevice ModelingElectrical EngineeringElectronic DevicesEngineering	2014	17
Ultimate MRAM Scaling: Design Exploration of High-Density, High-Performance and Energy-Efficient VGSOT for Last Level Cache Mohit Gupta, Yang Xiang, Fernando Garćıa-Redondo,	2023	16

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