2024 · 12 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSemiconductor MaterialsDevice ModelingDevice ReliabilityElectrical CharacterizationFerroelectric MaterialsMetal-oxide-semiconductor Field-effect TransistorsSemiconductor ReliabilityCharge TrappingCharge Trapping EffectsCharge Trapping ReliabilityCharge TrapsEnduranceFerroelectric Field-effect TransistorsWear-out MechanismsWear-out Modeling
In this work, we examine one of the important wear-out effects in metal-ferroelectric-insulator-semiconductor (MFIS) ferroelectric FETs (FeFET), comparing n-type and p-type endurance cycling degradation of the devices and propose a sloshing bathtub model as physical explanation for this effect. We show that: i) polarization (P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> ) switching is the main source of cycling degradation as demonstrated by severe V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> -walkout through bipolar cycling with P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> switching pulses, while much less degradation without P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf> switching, thus uni-polar pulsing, is observed; ii) comparing n-type and p-type cycling data, especially the n-type cycling degradation depends on the amount of interface trapped charge during the switching event, thus once ferroelectric (FE) bulk defects are fully charged up, electrons pile up at the FE/interlayer (FE/IL) interface, resulting in a steep V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> increase; iii) a sloshing bathtub model is well-suited to explain the endurance degradation and can reproduce observed data; iv) this model can also explain a trapping artefact in HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -based MFIS/MFIM structures, often mistakenly interpreted as ferroelectric wake-up.
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FeFET: A versatile CMOS compatible device with game-changing potential
Sven Beyer, Stefan Dünkel, Martin Trentzsch et al. · 2020 · 145 citations
Engineering, Computer Engineering, Electrical Engineering +15
2014 Symposium on VLSI Technology
IEEE Journal of Solid-State Circuits · 2014 · 137 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +12