7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS

Abstract

Extra-short-reach (XSR) serializer-deserializer (SerDes) transceivers for >100 Gb/s data rates have been developed in recent years [1–4]. Differing from the medium-reach (MR) or long-reach (LR) applications, the XSR TRX targets <50 mm traces for in-package die-to-die communication and optical I/O interfaces for co-packaged optics (CPO). Such a channel presents <10dB Nyquist loss when delivering a 112Gb/s PAM-4 signal. As a result, the equalization complexity can be reduced to achieve better power efficiency. In this work, a power-efficient XSR TRX architecture is presented and realized in 28nm CMOS consuming 2.16pJ/b with under 8.5dB loss.