6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology

Abstract

Explosive growth in mega-scale data centers drives switch chips to transition from 12.8Tb/s to 51.2Tb/s throughput. A 51.2Tb/s switch requires 512 lanes operating at 106Gb/s PAM-4. Such a massive integration of electrical SERDES is restrained by three factors: First, a large switch die size (>25×25mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) substantially lowers yield and prohibitively increases cost. Second, a large-size package suffers more than 10dB insertion loss from combined TX and RX traces. Considering practical equalization capabilities of a long-reach system (>30dB), 10dB package loss significantly limits the available channel reach. Lastly, channel reflection and cross-talk are excessive at 100Gb/s, which puts a ceiling on attainable BER.