Serdes Architecture

SerDes Architecture is a specialized I/O architecture that integrates a serializer and deserializer in a single module to convert parallel data streams into serial bit streams for high-speed transmission and vice versa, enabling efficient data communication between integrated circuits.

90

Publications

3.1K

Citations

708

Authors

82

Institutions

Publications per year

2017–2026

28

Authors

708

  1. EC
    E-Hung Chen

    Rambus (United States), United States

    4 publications · 173 citations

    4

    h-index

  2. PH
    P.C. Hunt

    University of Northampton, United Kingdom

    3 publications · 219 citations

    3

    h-index

  3. JF
    Jun Fan

    Missouri University of Science and Technology, United States

    2 publications · 42 citations

    3

    h-index

  4. AC
    Ariel Cohen

    Intel (Israel), Israel

    2 publications · 111 citations

    3

    h-index

  5. RS
    R. S. Simpson

    University of Northampton, United Kingdom

    3 publications · 219 citations

    3

    h-index

1–5 of 708

Venues

  1. IEEE Journal of Solid-State Circuits

    11 publications · 481 citations

    11

    h-index

  2. Journal of Instrumentation

    JINST · 2 publications · 103 citations

    2

    h-index

  3. IBM Journal of Research and Development

    2 publications · 56 citations

    2

    h-index

  4. 2

    h-index

  5. Proceedings/Proceedings - International Test Conference

    ITC · 1 publications · 45 citations

    1

    h-index

1–5