Serdes Architecture
SerDes Architecture is a specialized I/O architecture that integrates a serializer and deserializer in a single module to convert parallel data streams into serial bit streams for high-speed transmission and vice versa, enabling efficient data communication between integrated circuits.
90
Publications
3.1K
Citations
708
Authors
82
Institutions
Publications per year
2017–2026
28
Parents
90
BAG2: A process-portable framework for generator-based AMS circuit design
Eric Chang, Jaeduk Han, Woorham Bae et al. · 2018 · 125 citations
Engineering, Computer Engineering, Electrical Engineering +17
S. Baron, R. Ballabriga, S. Bonacini et al. · CERN Document Server (European Organization for Nuclear Research) · 2009 · 121 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +16
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82
Intel (United States)
Santa Clara, United States
6 h-index
25 publications
1.2K citations
NEC (Japan)
Tokyo, Japan
4 h-index
32 publications
759 citations
Rambus (United States)
Sunnyvale, United States
4 h-index
36 publications
531 citations
IBM (United States)
Armonk, United States
4 h-index
7 publications
177 citations
Intel (Israel)
Kiryat Gat, Israel
4 h-index
14 publications
1.1K citations
Texas Instruments (United States)
Dallas, United States
4 h-index
21 publications
1.5K citations
Missouri University of Science and Technology
Rolla, United States
4 h-index
7 publications
155 citations
MediaTek (Taiwan)
Hsinchu, Taiwan
3 h-index
25 publications
1.8K citations
1–8 of 82
11 publications · 481 citations
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JINST · 2 publications · 103 citations
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2 publications · 56 citations
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2 publications · 55 citations
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ITC · 1 publications · 45 citations
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