1.2 kV Enhancement-Mode p-GaN Gate HEMTs on 200 mm Engineered Substrates

Abstract

Abstract-This letter experimentally demonstrates 1.2 kV normally-off p-GaN gate lateral high-electronmobility transistors (HEMTs) on 200 mm diameter engineered substrates. The fabricated p-GaN gate HEMT with optimum gate-drain spacing exhibits a threshold voltage (Vth) of 3.2 V, an ON/OFF ratio of 108, low specific ON-resistance (Ron,sp) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.8 \mathrm{~m} \Omega-\mathrm{cm}^2$ </tex-math></inline-formula> and hard breakdown voltage (Vbd) at 1800 V. Optimized devices also show good wafer scale uniformity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma_{\text {Ron }}=1.2 \%$ </tex-math></inline-formula> ) for the evaluated electrical parameters and passed on-wafer high temperature gate bias (HTGB) and reverse bias stress tests without device failures.