Physical-aware Interconnect Testing and Repairing of Chiplets

Abstract

As the interconnect density of chiplets increases rapidly, some physics related defects appeared, such as coupling defects, etc. These defects are hard to detect with ordinary pseudo-random sequence patterns, some special test patterns are needed. Besides, the chip warpage caused by the thinning of 3D chips manufacturing and the uneven stress around TSVs or micro bumps will bring clustered faults of interconnections. For these defects, the repair rate of conventional interconnect redundancy method will be decreased. This paper proposes a physical-aware interconnect testing and repairing method of chiplets, using specific test patterns and clustered faults redundancy circuits to improve the interconnect test coverage and repair rate of chiplets. We also propose automatic repair circuits and the repair data synchronization scheme between multiple dies, so that the calculating and programming of repair data do not need to rely on the ATE programming, and the synchronization of the repair data between multiple dies can be done by hardware circuits automatically, which ensure the interconnection correctly after repairing.