IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2014 · 21 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSystem-on-chip DesignCmos Circuit DesignIntegrated Circuit DesignInterconnect DesignPhysical DesignStandard Cell DesignVery-large-scale Integration LayoutCircuit OptimizationDegradationMutual Coupling ReductionPlacement AlgorithmsStandard Cell PlacementThree-dimensional Integrated Circuit LayoutThrough-silicon Via DesignWirelength Optimization
Through silicon via (TSV) cross coupling can seriously degrade circuit performance of 3-D ICs if it is not considered during design. In this paper, we propose two algorithms which combine coupling-aware TSV placement with shield insertion to yield better results than either technique alone. We first introduce an algorithm for TSV placement assuming a fixed standard cell placement. The result of this algorithm is a 13% reduction in worst case coupling across all TSV pairs and a 90% reduction in the total number of TSV pairs violating an imposed coupling threshold. We then introduce a second algorithm that perturbs a given standard cell and TSV placement to improve coupling. This second algorithm yields a 17% reduction in worst case coupling and removes all coupling violations. Both algorithms cause wirelength (WL) to increase no more than 5%. Our algorithms offer a large improvement to TSV-TSV coupling at the expense of only a meager degradation of total WL, and in many designs and applications this trade-off is well justified.
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Tung-Chieh Chen, Zhewei Jiang, Tien-Chang Hsu et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2008 · 344 citations
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
Chang Liu, Taigon Song, Jonghyun Cho et al. · 2011 · 92 citations
Engineering, Computer Engineering, Electrical Engineering +17