An Advanced Full Adder Based Arithmetic Logic Unit (ALU) Using Low-Temperature Poly-Si Oxide TFTs

Abstract

This work presents a full adder-based CMOS arithmetic logic unit (ALU) made of p-type low-temperature poly-Si (LTPS) and n-type amorphous indium–gallium–zine oxide (a-IGZO) thin-film transistors (TFTs). The p-type TFT performs the maximum field-effect mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> ) of 70 cm2/V <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> s and subthreshold swing (SS) of 0.6 V/decade. The n-type TFT exhibits the mobility of 10.8 cm2/V <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> s and SS of 0.4 V/decade. The six-clock signals and three-supply voltage are employed to obtain a full output swing from high output voltage to low output voltage, where three clocks are used for selection operation mode and three clocks are input signals. For input swing of −15 to 15 V, constant high voltage of 15 V, and low voltage of 0 V, the proposed ALU shows a full output swing of 0–15 V with a fast fall time of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32~\mu \text{s}$ </tex-math></inline-formula> and a rise time of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64~\mu \text{s}$ </tex-math></inline-formula> in the worst situation. The proposed ALU is fully cascadable with five functionalities. The first LTPO CMOS-based ALU circuit demonstrates the potentiality of this emerging technology in logic operation.