Arithmetic Logic Unit Architecture

Arithmetic Logic Unit Architecture is a specialized computational framework within field-programmable gate array (FPGA) systems that defines the structural and operational organization of arithmetic and logic components to enable configurable, high-performance data processing tailored to specific algorithmic workloads.

908

Publications

29.6K

Citations

2.4K

Authors

686

Institutions

Publications per year

2017–2026

175

Authors

2.4K

  1. FD
    Florent de Dinechin

    École Normale Supérieure de Lyon, France

    9 publications · 591 citations

    9

    h-index

  2. ME
    M.D. Ercegovac

    University of California, Los Angeles, United States

    8 publications · 146 citations

    8

    h-index

  3. IV
    Ingrid Verbauwhede

    KU Leuven, Belgium

    8 publications · 224 citations

    8

    h-index

  4. MT
    Masamitsu Tanaka

    Nagoya University, Japan

    7 publications · 250 citations

    7

    h-index

  5. SK
    Seok‐Bum Ko

    University of Saskatchewan, Canada

    7 publications · 226 citations

    7

    h-index

1–5 of 2.4K

Venues

  1. IEEE Transactions on Computers

    47 publications · 2.8K citations

    31

    h-index

  2. IEEE Journal of Solid-State Circuits

    30 publications · 1.3K citations

    22

    h-index

  3. 20

    h-index

  4. IEEE Transactions on Applied Superconductivity

    15 publications · 514 citations

    13

    h-index

  5. Microprocessors and Microsystems

    MICPRO · 14 publications · 430 citations

    13

    h-index

1–5