Arithmetic Logic Unit Architecture
Arithmetic Logic Unit Architecture is a specialized computational framework within field-programmable gate array (FPGA) systems that defines the structural and operational organization of arithmetic and logic components to enable configurable, high-performance data processing tailored to specific algorithmic workloads.
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Jason Luu, Jeffrey Goeders, Michael Wainberg et al. · ACM Transactions on Reconfigurable Technology and Systems · 2014 · 362 citations
VLSI Architectures for Computing Multiplications and Inverses in GF(2<sup>m</sup>)
Wang, Troung, Shao et al. · IEEE Transactions on Computers · 1985 · 320 citations
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École Normale Supérieure de Lyon
Lyon, France
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31 publications
1.5K citations

Centre National de la Recherche Scientifique
Paris, France
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39 publications
2.2K citations

University of Toronto
Toronto, Canada
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4.1K citations
Nanyang Technological University
Singapore, Singapore
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IBM (United States)
Armonk, United States
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970 citations
Intel (United States)
Santa Clara, United States
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1.9K citations
University of California, Los Angeles
Los Angeles, United States
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794 citations
University of Southern California
Los Angeles, United States
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MICPRO · 14 publications · 430 citations
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