High-speed VLSI architectures for the AES algorithm

TLDR

The paper proposes novel high‑speed hardware architectures for implementing the Advanced Encryption Standard (AES) algorithm. The design replaces look‑up tables with combinational logic, employs composite‑field arithmetic to reduce area, compares subfield inversion implementations, and introduces an efficient key‑expansion module for subpipelined round units. The architecture eliminates LUT delay, enables subpipelining, and achieves 21.56 Gbps throughput with 79 % higher throughput‑per‑slice efficiency than the fastest prior FPGA implementation.

Abstract

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield GF(2/sup 4/) are compared. In addition, an efficient key expansion architecture suitable for the subpipelined round units is also presented. Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and is 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.