VLSI Architectures for Computing Multiplications and Inverses in GF(2<sup>m</sup>)

Wang, Troung, Shao, Deutsch, Omura, R Reed

IEEE Transactions on Computers · 1985 · 320 citations · 7 references

TL;DR

Finite‑field arithmetic underpins Reed‑Solomon coding and certain cryptographic schemes, and efficient multiplication and inversion algorithms are required for VLSI implementation, prompting the development of a normal‑basis Massey‑Omura multiplier. The paper proposes a pipeline architecture that implements the Massey‑Omura multiplier in GF(2^m) and extends it to compute field inverses. By exploiting the normal‑basis squaring property, the authors design a pipeline that performs multiplication and, with the same multiplier, computes inverses in GF(2^m). The resulting multiplier and inverse circuits are regular, simple, expandable, and well suited for VLSI deployment.

Abstract

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura [1] recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.

References

7