IEEE Electron Device Letters · 2010 · 182 citations · 15 references
EngineeringElectrical EngineeringPhysicsElectronic MaterialsMicroelectronicsSemiconductor DevicesDielectricsMetal-oxide-semiconductor Field-effect TransistorsOxide SemiconductorsSemiconductor ReliabilityThin-film TransistorsWide-bandgap Semiconductor DevicesBias Stress EffectsBias Stress InstabilityBias Temperature InstabilityGate Oxide DegradationGate Oxide ReliabilityReliability DegradationReliability Degradation MechanismsSemiconductor Stability
This letter examines the effect of the gate dielectric material on the light-induced bias-temperature instability of an In–Ga–Zn–O (IGZO) thin-film transistor (TFT). After applying positive and negative bias stresses, the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{SiN}_{x}$</tex></formula> -gated TFT exhibited inferior stability to the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{SiO}_{2}$</tex></formula> -gated TFT, which was explained by the charge trapping mechanism. However, light illumination under a negative bias stress accelerated the negative displacement of the threshold voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm th})$</tex></formula> of the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{SiN}_{x}$</tex></formula> -gated IGZO TFT compared to that of the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{SiO}_{2}$</tex></formula> -gated TFT. This was attributed to the injection of photocreated hole carriers into the underlying gate dielectric bulk region as well as the hole trapping at the gate/channel interface.
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