2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 55 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringDesign OptimizationLow-power DesignNanotechnologyCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyEnergy-efficient DesignIntegrated Circuit DesignPhysical DesignPower OptimizationDevice OptimizationLow-power Circuit DesignLow-power Cmos DesignSheet Metal DesignTrack System Design
We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.
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