C. Roda Neve

PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch

P. Schuddinck, F. M. Bufler, Yang Xiang et al. · 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 49 citations

Low-power Electronics, Electrical Engineering, Tight Gate Pitch +12

Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates

Khaled Ben Ali, C. Roda Neve, Ali Gharsallah et al. · IEEE Transactions on Electron Devices · 2011 · 40 citations

Electrical Engineering, Engineering, Physics +12

Advanced Si-based substrates for RF passive integration: Comparison between local porous Si layer technology and trap-rich high resistivity Si

Panagiotis Sarafis, E. Hourdakis, A. G. Nassiopoulou et al. · Solid-State Electronics · 2013 · 33 citations · Full text

Rf Passive Integration, Electrical Engineering, Engineering +10

RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications

C. Roda Neve, K. Ben Alia, C. Malaquin et al. · 2013 · 22 citations

Engineering, Linear Performance, Commercial 200 +16

RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer

Khaled Ben Ali, C. Roda Neve, Ali Gharsallah et al. · 2012 · 21 citations

Engineering, Integrated Circuits, Silicon On Insulator +18