2003 · 10 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringMemoryMicroelectronicsSemiconductor DevicesBuilt-in Self-testDevice ReliabilityMemory DevicesMemory Subsystem DesignAnalog Built-in Self-testLow-power Memory CircuitsMemory Built-in Self-repairMemory Built-in Self-testMemory Circuit DesignMemory CircuitsMemory TestMicroprocessor Built-in Self-test
A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
3
A Twisted Bit Line Technique for Multi-Mb Drams
Yoshihara, Hidaka, Fujishima · 1988 · 32 citations
Engineering, Computer Engineering, Electrical Engineering +8