1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) · 2003 · 87 citations · 18 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDesign OptimizationSystem-on-chip DesignBuffer ManagementIntegrated Circuit DesignInterconnect ArchitectureInterconnect DesignLayout OptimizationVery-large-scale Integration LayoutBuffer InsertionFeasible Design RegionFloorplanningIntegrated Circuit FloorplanningInterconnect Delay OptimizationInterconnect FloorplanningInterconnect OptimizationPlacement Algorithms
We study buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer insertion, and derive closed-form formula for FR. We observe that the FR for a buffer is quite large in general even under fairly tight delay constraints. Therefore, FR gives us a lot of flexibility to plan for buffer locations. We then develop an effective buffer block planning (BBP) algorithm to perform buffer clustering such that the overall chip area and the buffer block number can be minimized. To the best of our knowledge, this is the first in-depth study on buffer planning for interconnect-driven floorplanning with both area and delay consideration.
18
Performance optimization of VLSI interconnect layout
Jason Cong, Lei He, Cheng‐Kok Koh et al. · Integration · 1996 · 337 citations
Engineering, Computer Engineering, Electrical Engineering +12
Interconnect design for deep submicron ICs
Cong, Zhigang Pan, Lei He et al. · 1997 · 114 citations
Engineering, Computer Engineering, Electrical Engineering +17