Challenges and Opportunities for Design Innovations in Nanometer Technologies

The driving force behind the spectacular advancement of the integrated circuit technology in the past thirty years has been the exponential scaling of the feature size, i.e., the minimum dimension of a transistor. It has been following the Moore’s Law [1] at the rate of a factor of 0.7 reduction every three years. It is expected that such exponential scaling will continue for at least another 1012 years as projected in the recently published 1997 National Technology Roadmap for Semiconductors (NTRS’97) [2] shown in Table 1. This will lead to over half a billion transistors integrated on a single chip with an operating frequency of 2-3 GHz in the 70nm technology by Year 2009. The challenges to sustain such an exponential growth to achieve gigascale integration have shifted in a large degree, however, from the process and manufacturing technologies to the design technology. A great deal of design innovation, in terms of both significant extension of the existing design capability and the development of new design paradigm and methodology, is needed to achieve the projected targets in the NTRS’97. This paper discusses the challenges and opportunities for design innovations in the future IC designs, especially in the areas of interconnect design and high-degree of on-chip integration. Section 2 presents a number of design challenges in these areas, with quantitative measurements derived based on the technology projection in NTRS’97. Section 3 discusses opportunities and possible directions for design technology innovation to meet various design challenges in the road ahead.