Interconnect Floorplanning
Interconnect Floorplanning is a systematic design methodology within electronic system integration that determines the optimal spatial arrangement and routing architecture of interconnect components to minimize signal delay, power consumption, and area utilization while adhering to performance and manufacturability constraints.
61
Publications
3.1K
Citations
146
Authors
63
Institutions
Publications per year
2017–2026
0
Parents
61
Interconnect and thermal-aware floorplanning for 3D microprocessors
1–5 of 61
146
7
h-index
5
h-index
University of Illinois Urbana-Champaign, United States
5 publications · 225 citations
5
h-index
4
h-index
4
h-index
1–5 of 146
63

National Taiwan University
Taipei, Taiwan
7 h-index
13 publications
779 citations

University of Minnesota
Minneapolis, United States
6 h-index
16 publications
580 citations
University of California, Los Angeles
Los Angeles, United States
5 h-index
13 publications
1K citations
Chinese University of Hong Kong
Hong Kong, Hong Kong
4 h-index
8 publications
178 citations
Intel (United States)
Santa Clara, United States
4 h-index
8 publications
294 citations
Politecnico di Torino
Turin, Italy
3 h-index
6 publications
174 citations
Purdue University West Lafayette
West Lafayette, United States
3 h-index
6 publications
336 citations
University of Illinois Urbana-Champaign
Urbana, United States
3 h-index
4 publications
157 citations
1–8 of 63
10 publications · 532 citations
10
h-index
Conference · 2 publications · 99 citations
2
h-index
Conference · 1 publications · 44 citations
1
h-index
1 publications · 19 citations
1
h-index
Conference · 1 publications · 19 citations
1
h-index
1–5