Concepedia

Integrated Circuit Floorplanning

Integrated Circuit Floorplanning is a physical design methodology that determines the approximate positions of circuit components and interconnects on a chip to optimize performance, area, and power within predefined design constraints.

218

Publications

10.1K

Citations

501

Authors

156

Institutions

Publications per year

2017–2026

18

Parents

Publications

218

Simulated annealing algorithms: an overview

Rob A. Rutenbar · IEEE Circuits and Devices Magazine · 1989 · 799 citations

, , +13

A thermal-driven floorplanning algorithm for 3D ICs

Jie Wei, Yan Zhang · 2005 · 431 citations

, , +16

Automatic Floorplan Design

Ralph H. J. M. Otten · Design Automation Conference · 1982 · 310 citations

, , +17

Corner block list: an effective and efficient topological representation of non-slicing floorplan

Xianlong Hong, Gang Huang, Yici Cai et al. · 2000 · 303 citations

, , +16

Defect tolerance in VLSI circuits: techniques and yield analysis

Israel Koren, Zahava Koren · Proceedings of the IEEE · 1998 · 233 citations

, , +17

1–5 of 218

Authors

501

  1. MD
    Martin D. F. Wong

    University of Illinois Urbana-Champaign, United States

    15 publications · 564 citations

    14

    h-index

  2. YC
    Yao‐Wen Chang

    National Taiwan University, Taiwan

    11 publications · 578 citations

    11

    h-index

  3. SK
    Sung Kyu Lim

    Georgia Institute of Technology, United States

    8 publications · 457 citations

    8

    h-index

  4. XH
    Xianlong Hong

    Tsinghua University, China

    7 publications · 584 citations

    7

    h-index

  5. EF
    Evangeline F. Y. Young

    Chinese University of Hong Kong, Hong Kong SAR China

    6 publications · 169 citations

    6

    h-index

1–5 of 501

Institutions

156

  1. Tsinghua University

    Beijing, China

    13 h-index

    52 publications

    3.4K citations

  2. The University of Texas at Austin

    Austin, United States

    11 h-index

    29 publications

    915 citations

  3. National Taiwan University

    Taipei, Taiwan

    11 h-index

    20 publications

    1.1K citations

  4. Chinese University of Hong Kong

    Hong Kong, Hong Kong

    10 h-index

    14 publications

    401 citations

  5. Intel (United States)

    Santa Clara, United States

    10 h-index

    23 publications

    880 citations

  6. University of California, Los Angeles

    Los Angeles, United States

    10 h-index

    26 publications

    2.3K citations

  7. University of California San Diego

    San Diego, United States

    10 h-index

    17 publications

    786 citations

  8. University of Illinois Urbana-Champaign

    Urbana, United States

    10 h-index

    16 publications

    581 citations

1–8 of 156

Venues

  1. 18

    h-index

  2. 7

    h-index

  3. International Conference on Computer Aided Design

    Conference · 5 publications · 215 citations

    5

    h-index

  4. Integration

    5 publications · 150 citations

    5

    h-index

  5. Design Automation Conference

    Conference · 4 publications · 343 citations

    4

    h-index

1–5