Corner block list: an effective and efficient topological representation of non-slicing floorplan

Xianlong Hong, Gang Huang, Yici Cai, +4

International Conference on Computer Aided Design

EngineeringVlsi DesignGeometryComputer ArchitectureSubdivision Surface +18

Corner block list: an effective and efficient topological representation of non-slicing floorplan

Xianlong Hong, Gang Huang, Yici Cai, +4

EngineeringVlsi DesignGeometryComputer ArchitectureSubdivision Surface +18

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, +5

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

EngineeringElectronic Design AutomationComputer ArchitectureComputer-aided DesignStructural Optimization +14

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs

Bin Liu, Yici Cai, Qiang Zhou, +1

EngineeringVlsi DesignPower Optimization (Eda)Computer ArchitectureStandard Cell Placement +14

VLSI floorplanning with boundary constraints based on corner block list

Yuchun Ma, Sheqin Dong, Xianiong Hong, +3

Geometric ModelingPhysical Design (Electronics)EngineeringGeometric Constraint SolvingSimulated Annealing +13

Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips

Qin Wang, Shiliang Zuo, Hailong Yao, +4

Flow ControlEngineeringMicrofabricationBioelectronicsComputer Engineering +12

Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips

Qin Wang, Hao Zou, Hailong Yao, +3

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Flow ControlEngineeringFluid MechanicsComputer ArchitectureFlow-based Microfluidic Biochips +18

Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks

Xiaoyi Wang, Hongyu Wang, Jian He, +3

EngineeringPower ElectronicsInterconnect (Integrated Circuits)Reliability EngineeringElectric Power Transmission +19

Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction

Weixiang Shen, Yici Cai, Xianlong Hong, +1

Cluster ComputingEngineeringVlsi DesignClock Tree PowerComputer Architecture +17

Control-fluidic CoDesign for paper-based digital microfluidic biochips

Qin Wang, Zeyan Li, Haena Cheong, +7

Control-fluidic CodesignEngineeringFlexible ElectronicsMicrofabricationNew Design Challenge +12