2002 · 35 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsVlsi DesignClock ManagementDelay ModelingEmbedded Memory BlocksMemory Subsystem DesignTiming AnalysisFirst In First OutFirst-in First-out BuffersHigh-speed Cmos DesignSynchronous Circuit Design
A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.
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