Statistics
Publications
1
Citations
35
H-Index
1
Active since
2002
Affiliations
NEC (Japan)(Current)
T. Matano is an author at NEC (Japan) specializing in first-in first-out buffers, electrical engineering, and engineering.
Publications per year
2002–2002
1
1
A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay
T. Saeki, Y. Nakaoka, M. Fujita et al. · 2002 · 35 citations
Engineering, Computer Engineering, Electrical Engineering +12
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