Statistics
Publications
2
Citations
48
H-Index
2
Active since
2002
Affiliations
NEC (Japan)(Current)
Y. Nakaoka is an author at NEC (Japan) specializing in computer architecture, delay modeling, and memory subsystem design.
Publications per year
2002–2012
2
2
A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay
T. Saeki, Y. Nakaoka, M. Fujita et al. · 2002 · 35 citations
Engineering, Computer Engineering, Electrical Engineering +12
SESSION 69: EMBRYOLOGY - CAUSE AND EFFECT OF BAD TIMING
Charlene Hickman, A. Campbell, Sean Duffy et al. · Human Reproduction · 2012 · 13 citations
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