Publication | Open Access
Experimental Extraction and Simulation of Charge Trapping During Endurance of FeFET With TiN/HfZrO/SiO<sub>2</sub>/Si (MFIS) Gate Structure
51
Citations
35
References
2022
Year
Device ModelingGate StructureElectrical EngineeringCharge TrappingEndurance Fatigue ProcessEngineeringSemiconductor DeviceTrapped ChargesStress-induced Leakage CurrentEndurance FatigueCondensed Matter PhysicsApplied PhysicsExperimental ExtractionMicroelectronicsElectrical Insulation
We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window (MW) decreases: 1) the ferroelectric characteristic of Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is not degraded; 2) the trap density in the upper bandgap of the gate stacks increases; and 3) the reason for MW decrease is increased trapped electrons after program operation but not related to hole trapping/detrapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process.
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